High speed, low power, isolated multiplexer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 20, 2016
Grant Date -
Apr 2, 2015
app pub date -
Sep 30, 2013
filing date -
Sep 30, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully