Current change mitigation policy for limiting voltage droop in graphics logic
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United States of America Patent
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Feb 2, 2016
Grant Date -
Apr 2, 2015
app pub date -
Sep 27, 2013
filing date -
Sep 27, 2013
priority date (Note) -
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Abstract
Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.
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