Method and devices for time and frequency synchronization using a phase locked loop
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United States of America Patent
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Dec 27, 2016
Grant Date -
Apr 2, 2015
app pub date -
Oct 2, 2013
filing date -
Oct 2, 2013
priority date (Note) -
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Abstract
This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.
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