MEMORY SYSTEM

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20150095556A1
SERIAL NO

14195765

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Abstract

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A memory system includes a first memory chip, a second memory chip, and a memory controller. The first memory chip and the second memory chip are connected to the memory controller via a plurality of data lines including a first data line and a second data line. The first memory chip is configured to outputs status information via the first data line to the memory controller. The second memory chip is configured to output status information via the second data line to the memory controller at the same time as the first memory chip.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
GOTO, Hiroyuki Kanagawa, JP 94 1189
TAKEDA, Shinya Kanagawa, JP 74 250
TOUHATA, Akihito Kanagawa, JP 3 4

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