Method of eliminating poor reveal of through silicon vias
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United States of America Patent
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Sep 13, 2016
Grant Date -
Apr 16, 2015
app pub date -
Oct 11, 2013
filing date -
Oct 11, 2013
priority date (Note) -
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Abstract
A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.
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