Decoupling circuit and semiconductor integrated circuit
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United States of America Patent
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Jun 28, 2016
Grant Date -
Apr 16, 2015
app pub date -
Dec 18, 2014
filing date -
Apr 23, 2010
priority date (Note) -
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Abstract
A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.
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