CDR circuit and serial communication interface circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9203601
APP PUB NO 20150103964A1
SERIAL NO

14465477

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Abstract

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The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kousai, Shouhei Yokohama Kanagawa, JP 42 205
Miyashita, Daisuke Kawasaki Kanagawa, JP 65 368
Wadatsumi, Junji Ota Tokyo, JP 10 25

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