Three-dimensional charge trapping NAND cell with discrete charge trapping film
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United States of America Patent
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Nov 29, 2016
Grant Date -
Apr 23, 2015
app pub date -
Oct 17, 2013
filing date -
Oct 17, 2013
priority date (Note) -
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Abstract
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
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