Structures and methods for monitoring dielectric reliability with through-silicon vias

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United States of America Patent

PATENT NO 9404953
APP PUB NO 20150115982A1
SERIAL NO

14068273

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Abstract

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Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fen Williston, US 112 767
Farooq, Mukta G Hopewell Junction, US 212 3354
Griesemer, John A Salt Point, US 11 100
Kothandaraman, Chandrasekharan Hopewell Junction, US 139 1247
Safran, John Matthew Wappingers Falls, US 7 86
Sullivan, Timothy Dooling Underhill, US 22 226

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