System and method for improving memory performance and identifying weak bits

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United States of America Patent

PATENT NO 9543044
APP PUB NO 20150127998A1
SERIAL NO

14074341

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Abstract

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According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

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Patent Owner(s)

  • STMICROELECTRONICS S.R.L.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chhabra, Amit Delhi, IN 37 109
Jain, Abhishek Delhi, IN 149 713
Veggetti, Andrea Mario Agrate Brianza, IT 4 17

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