Vertical 1T-1R memory cells, memory arrays and methods of forming the same
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United States of America Patent
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Aug 4, 2015
Grant Date -
May 14, 2015
app pub date -
Nov 8, 2013
filing date -
Nov 8, 2013
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Abstract
Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.
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