BIAS CIRCUIT USING NEGATIVE VOLTAGE
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United States of America Patent
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Issued Date -
May 21, 2015
app pub date -
Jun 19, 2014
filing date -
Nov 21, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.
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