Computer memory power management
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United States of America Patent
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Aug 25, 2015
Grant Date -
May 21, 2015
app pub date -
Apr 8, 2014
filing date -
Nov 21, 2013
priority date (Note) -
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Abstract
A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.
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