Error-correcting code distribution for memory systems
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United States of America Patent
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Nov 17, 2015
Grant Date -
May 21, 2015
app pub date -
Nov 19, 2013
filing date -
Nov 19, 2013
priority date (Note) -
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Abstract
According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
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