USE OF A CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
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United States of America Patent
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Issued Date -
May 28, 2015
app pub date -
Jun 6, 2013
filing date -
Jun 7, 2012
priority date (Note) -
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Abstract
Integrated circuit assemblies, as well as methods for creating the same, are provided. The integrated circuit assembly includes a first chip and a second chip, including respective face surfaces, wherein the first chip and the second chip are bonded in a face-against-face contact configuration. The integrated circuit assembly includes a via disposed to pass through the first chip and the second chip. The via is surrounded by at least one material of the respective first chip and the second chip. A cushion layer encapsulating at least a portion of the via is formed between the via and the at least one material surrounding the via.
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