Multiple active vertically aligned cores for three-dimensional chip stack
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United States of America Patent
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Apr 12, 2016
Grant Date -
Jun 11, 2015
app pub date -
May 15, 2014
filing date -
Dec 5, 2013
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Abstract
An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus.
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