Methods of forming sidewall gates

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United States of America Patent

PATENT NO 9177964
APP PUB NO 20150162338A1
SERIAL NO

14099084

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Abstract

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A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES LLC5080 SPECTRUM DRIVE SUITE 1050W ADDISON TX 75001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mine, Teruyuki Yokkaichi Mie, JP 14 174
Nakada, Akira Yokkaichi Mie, JP 89 1551
Sano, Michiaki Aichi ken, JP 46 758
Yanagida, Naohito Yokkaichi Mie, JP 6 180

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