Semiconductor integrated circuit device and method for designing layout of the same having standard cells, basic cells and a protective diode cell
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United States of America Patent
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Aug 30, 2016
Grant Date -
Jun 25, 2015
app pub date -
Dec 18, 2014
filing date -
Dec 24, 2013
priority date (Note) -
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Abstract
A method for designing a layout of a semiconductor integrated circuit device includes placing a plurality of standard cells respectively constituting a plurality of functional blocks in a part of a logic circuit placement region, placing a plurality of basic cells in a part of regions of the logic circuit placement region in which no standard cells are placed, and placing at least one diode cell in at least a part of regions of the logic circuit placement region in which no standard cells and no basic cells are placed, the diode cell including a first and a second diode, the first diode being connected between a gate electrode of a predetermined transistor and a first power supply line and the second diode between the gate electrode and a second power supply line.
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