CLOCK ASSIGNMENTS FOR PROGRAMMABLE LOGIC DEVICE
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United States of America Patent
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Issued Date -
Jun 25, 2015
app pub date -
Dec 20, 2013
filing date -
Dec 20, 2013
priority date (Note) -
Abandoned
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Abstract
Various techniques are provided to perform clock assignments in a programmable logic device (PLD). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD), synthesizing the design into a plurality of components of the PLD configured to perform the operations, and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD. Additional methods, systems, machine-readable mediums, and other techniques are also provided.
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