Graphics voltage reduction for load line optimization

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United States of America Patent

PATENT NO 9514715
APP PUB NO 20150179146A1
SERIAL NO

14139031

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Abstract

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Technologies are presented that optimize graphics power-performance efficiency. A method of graphics processing may include beginning a graphics workload with a first voltage and a first clamping threshold; monitoring amounts of time that bursts of dynamic capacitance remain above the first clamping threshold; and, if the dynamic capacitance remains above the first clamping threshold for more than a predetermined time threshold, setting the voltage to a second voltage and setting the clamping threshold to a second clamping threshold until the end of the frame. If, at the end of an initial frame, a number of clock cycles from a start of the frame to when the predetermined time threshold is exceeded is less than a predetermined minimum number of clock cycles, the second clamping threshold and the second voltage may be maintained for processing of a predetermined number of subsequent frames.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hurd, Linda L Cool, US 90 656

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