Memory system including PE count circuit and method of operating the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 17, 2018
Grant Date -
Jul 2, 2015
app pub date -
Dec 27, 2013
filing date -
Dec 27, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully