System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks
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United States of America Patent
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Jul 12, 2016
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app pub date -
Dec 26, 2013
filing date -
Dec 26, 2013
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Abstract
An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.
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