Nonvolatile semiconductor memory device
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United States of America Patent
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May 17, 2016
Grant Date -
Jul 2, 2015
app pub date -
Mar 12, 2015
filing date -
Oct 30, 2012
priority date (Note) -
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Abstract
A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.
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