Input buffer for semiconductor memory device and flash memory device including the same
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United States of America Patent
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Apr 12, 2016
Grant Date -
Jul 2, 2015
app pub date -
Dec 2, 2014
filing date -
Dec 26, 2013
priority date (Note) -
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Abstract
An input buffer includes an amplifier circuit configured to amplify an input signal and output an amplified signal to a first output node. The input signal is amplified according to a first bias voltage set, at a bias node, to a first level based on a power supply voltage and a reference voltage. The input buffer includes an output circuit configured to receive and buffer the amplified signal and output an output signal to a second output node. The input buffer includes a dynamic bias voltage generator configured to change the first bias voltage to a second level in response to a transition of the output signal.
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