Double-sided segmented line architecture in 3D integration

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United States of America Patent

PATENT NO 9559040
SERIAL NO

14143015

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Abstract

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Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Batra, Pooja R White Plains, US 6 32
Golz, John W Manassas, US 14 142
Jacunski, Mark Colchester, US 2 20
Kirihata, Toshiaki Poughkeepsie, US 150 2342

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