Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damage

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United States of America Patent

PATENT NO 9601921
SERIAL NO

14142607

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Abstract

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Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (FETs), a first internal node, a second internal node, a first output node and a second output node. A node isolation circuit is connected to the first output node and the second output node of the tie-off circuit. The node isolation circuit includes a first FET with a third output node and a second FET with a fourth output node. The third output node and the fourth output node are electrically isolated from the first internal node and the second internal node.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Guo, Chen San Jose, US 27 51
Nakamura, Yutaka Kyoto, JP 199 2435
Sawada, Jun Austin, US 86 624

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