Equalization for high speed input/output (I/O) link

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United States of America Patent

PATENT NO 9335933
APP PUB NO 20150188732A1
SERIAL NO

14142619

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Abstract

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Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (ISI) in high speed input/output (I/O) interfaces. Data dependent jitter (DDJ) compensation techniques that may be utilized in the transmission or receiving circuitry of the I/O interface, including capturing bit data values of a data signal prior to an identified data transition, and delaying/advancing the transmission/reception the data signal or a corresponding clock signal based on these bit data values.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Charlie Cupertino, US 14 154
Muljono, Harry San Ramon, US 59 618
Sun, Linda K Fremont, US 6 21
Xiao, Kai University Place, US 170 594

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