Constructing a logical tree topology in a parallel computer
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United States of America Patent
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Nov 15, 2016
Grant Date -
Jul 9, 2015
app pub date -
Apr 30, 2014
filing date -
Jan 6, 2014
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Abstract
Constructing a logical tree topology in a parallel computer that includes compute nodes, where each compute node includes a hardware acceleration unit and executes an identical number of tasks and the tasks of each node have a rank, includes: creating hardware acceleration groups, with each hardware acceleration group including one task from each node, where the one task from each node has the same rank; assigning one task of a root compute node as a global root of the logical tree topology; assigning tasks of the root compute node other than the global root as local children of the global root; and assigning each of the global root and local children of the root compute node as a root of a subtree of tasks, wherein each subtree comprises the tasks of a hardware acceleration group.
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