Implementing ECC control for enhanced endurance and data retention of flash memories
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United States of America Patent
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Apr 5, 2016
Grant Date -
Jul 16, 2015
app pub date -
Jun 16, 2014
filing date -
Jan 10, 2014
priority date (Note) -
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Abstract
A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.
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