Pulsed laser anneal process for transistors with partial melt of a raised source-drain
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United States of America Patent
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Sep 13, 2016
Grant Date -
Jul 16, 2015
app pub date -
Mar 24, 2015
filing date -
Dec 19, 2011
priority date (Note) -
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Abstract
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.
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