PROGRAMMABLE LOGIC DEVICE AND VERIFICATION METHOD THEREFOR
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United States of America Patent
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Issued Date -
Jul 23, 2015
app pub date -
Sep 11, 2013
filing date -
Sep 14, 2012
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Abandoned
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Abstract
Provided are: a programmable logic device capable of efficiently verifying whether an internal status of each sequential circuit makes transition equivalent to that of a logic program written in a hardware description language (HDL); and a verification method for the programmable logic device.
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