Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 17, 2016
Grant Date -
Jul 23, 2015
app pub date -
Jan 22, 2014
filing date -
Jan 22, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully