Multi-core architecture for low latency video decoder

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United States of America Patent

PATENT NO 9661339
APP PUB NO 20150208076A1
SERIAL NO

14174183

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Abstract

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An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barazesh, Bahman Flemington, US 19 191
Tan, Mizhou Basking Ridge, US 12 126

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