METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION

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United States of America Patent

APP PUB NO 20150214097A1
SERIAL NO

14413966

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention provides a method for manufacturing a shallow trench isolation, comprising: forming a hard mask layer on the substrate; phottoetching/etching the hard mask layer and the substrate to form a plurality of first trenches along a first direction and a plurality of second trenches along a second direction perpendicular to the first direction, wherein the volume of the second trench is greater than that of the first trench; depositing an insulating material in the first and second trenches; planarizing the insulating material and the hard mask layer until the substrate is exposed so as to form a shallow trench isolation. According to a method of the present invention, the shallow trench isolation is allowed by etch-filling to be deep and wide in the channel width direction and shallow and narrow in the channel length direction, and stress is applied to NMOS and PMOS simultaneously to increase the carrier mobility of the channel region, thereby improving the overall driving capability of the device.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES100029 BEIJING CITY CHAOYANG DISTRICT BEITUCHENG WEST ROAD NO 3 CHINESE ACADEMY OF SCIENCES INSTITUTE OF MICROELECTRONICS MUNICIPAL DISTRICT BEIJING CITY 100029

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Yin, Haizhou Poughkeepsie, US 241 2072
Zhang, Keke Shandong, CN 13 53

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