CHIP STACK, SEMICONDUCTOR DEVICES HAVING THE SAME, AND MANUFACTURING METHODS FOR CHIP STACK
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 30, 2015
app pub date -
Aug 21, 2013
filing date -
Aug 27, 2012
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A chip stack (11) is configured by stacking at least first, second, and third semiconductor chips (10a, 10b, 10c). The first semiconductor chip (10a) has bump electrodes formed only on one side thereof. The second semiconductor chip (10b) has bump electrodes formed on both sides thereof and they are electrically connected each other. The second semiconductor chip (10b) is stacked on and electrically connected to the first semiconductor chip (10a) through a first solder layer. The third semiconductor chip (10c) has bump electrodes formed on both sides thereof and they are electrically connected each other. Second and third solder layers are formed on the bump electrodes on the both sides of the third semiconductor chip. The third semiconductor chip (10c) is stacked on and electrically connected to the second semiconductor chip (10b) through the third solder layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully