Stacked chip device
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United States of America Patent
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Aug 30, 2016
Grant Date -
Jul 30, 2015
app pub date -
Jan 28, 2015
filing date -
Jan 29, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.
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