Method for generating clock for system operating at rising edge
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United States of America Patent
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Dec 1, 2015
Grant Date -
Jul 30, 2015
app pub date -
Oct 27, 2014
filing date -
Jan 27, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A method of converting an input clock to generate an output clock and providing a certain system with the output clock is provided. The method includes setting up a desired output clock value and a variable value and determining whether the input clock is the rising edge; adding the output clock value to the variable value to provide a calculated value when the input clock is the rising edge; comparing the calculated value with the input clock value; and outputting, when the calculated value is equal to or larger than the input clock value as a result of comparison, the output clock as logic state ‘1’ and setting, a value obtained by subtracting the input clock value from the calculated value, as the variable value.
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