Device and method for packet processing with memories having different latencies
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United States of America Patent
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Jan 29, 2019
Grant Date -
Jul 30, 2015
app pub date -
Jan 23, 2015
filing date -
Jan 30, 2014
priority date (Note) -
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Abstract
A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.
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