HIGH-BANDWIDTH DRAM USING INTERPOSER AND STACKING
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United States of America Patent
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Issued Date -
Aug 6, 2015
app pub date -
Feb 5, 2015
filing date -
Feb 6, 2014
priority date (Note) -
Abandoned
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Abstract
Embodiments of the present disclosure provide a packaging arrangement that comprises an interposer and a system on chip (SoC) die disposed on the interposer. The packaging arrangement also comprises a plurality of memory dies stacked on one another to provide a stack of memory dies. A bottom memory die of the stack of memory dies is disposed on the substrate adjacent to the SoC die. Each memory die includes input/output (I/O) pads, wherein the I/O pads of a corresponding memory die are located on only one side of the corresponding memory die. The plurality of memory dies is stacked on one another such that all of the I/O pads are arranged along a same side of the stack of memory dies. The plurality of memory dies is also stacked such that all the I/O pads are exposed.
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