Importance

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Abstract

Disclosed herein is a semiconductor device that includes a semiconductor chip. The semiconductor chip includes a plurality of memory units each including a plurality of memory cells. The semiconductor chip further includes a plurality of pad groups each coupled to a corresponding one of the memory units and each including a plurality of pads, and a plurality of test pads each coupled in common to the memory units. In a normal operation mode, the test pads are free from signals and the pads of each of the pad groups are supplied with signals such that normal operations are performed respectively on the memory units. In a test operation mode, the test pads are supplied with test signals and the pads of each of the pad groups are free from signals such that test operations are performed respectively on the memory units.

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First Claim