Structure for finFET CMOS
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United States of America Patent
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Feb 21, 2017
Grant Date -
Aug 13, 2015
app pub date -
Apr 23, 2015
filing date -
Mar 21, 2013
priority date (Note) -
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Abstract
According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.
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