Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
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United States of America Patent
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Apr 19, 2016
Grant Date -
Aug 13, 2015
app pub date -
Feb 28, 2014
filing date -
Feb 11, 2014
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Abstract
An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
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