SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20150235689A1
SERIAL NO

14601975

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Abstract

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A semiconductor memory device includes: a memory cell array including a memory cell, which includes a ferroelectric capacitor and an access transistor which is a first conductive type transistor formed in a second conductive type well and includes a source or a drain connected to one electrode of the ferroelectric capacitor; and a control circuit which controls a potential applied to the second conductive type well. The control circuit applies a fixed potential to another electrode of the ferroelectric capacitor and applies a second potential being a forward voltage with respect to a junction between the first conductive type source and drain and the second conductive type well when erasing data in the memory cell, and applies a third potential not being the forward voltage with respect to the junction between the first conductive type source and drain and the second conductive type well in a normal operation.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU SEMICONDUCTOR LIMITED2-10-23 SHIN-YOKOHAMA KOHOKU-KU YOKOHAMA-SHI KANAGAWA 222-0033

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
KAWASHIMA, Shoichiro Yokohama, JP 35 511

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