ACCELERATION SYSTEM IN 3D DIE-STACKED DRAM
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United States of America Patent
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Issued Date -
Aug 27, 2015
app pub date -
Jan 30, 2015
filing date -
Feb 24, 2014
priority date (Note) -
Abandoned
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Abstract
Provided is a memory device including a logic layer including at least one of a peripheral device, an interface, and a built-in self-test (BIST) module and a reconfigurable accelerator (RA), and at least one data layer to store data, wherein the RA is positioned in a vacant space of the logic layer and processes at least a portion of a task processed by the memory device.
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