Importance

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Abstract

Embodiments of the invention provide a power reduction device and method. According to at least one embodiment, there is provided a power reduction device, which includes an internal reset generating unit outputting an internal reset signal when a power supplying voltage is lowered from a normal state to a lower threshold voltage or less, and a power controlling unit outputting a power down signal after a predetermined time elapses when the internal reset signal is output from the internal reset generating unit. According to at least one embodiment, a power down mode in a chip is operated when a power lower than a reference is provided for a long time, thereby making it possible to reduce a current consumed in the chip.

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First Claim