ERROR CORRECTION DECODER
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United States of America Patent
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Issued Date -
Sep 10, 2015
app pub date -
Mar 7, 2014
filing date -
Dec 3, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.
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