Non-volatile semiconductor memory device and manufacturing method of p-channel MOS transistor
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United States of America Patent
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Nov 26, 2019
Grant Date -
Sep 10, 2015
app pub date -
Feb 24, 2015
filing date -
Mar 7, 2014
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Abstract
A non-volatile semiconductor memory device includes a memory cell transistor having a memory cell capable of writing and erasing data, and a peripheral circuit that drives the memory cell which includes a first p-channel MOS transistor including a gate electrode that is formed on a semiconductor layer with a first gate insulation film therebetween, a channel region that is formed on a surface of the semiconductor layer and has a first peak dopant concentration, a source region and a drain region that have a second peak dopant concentration higher than the first peak dopant concentration, and overlap regions that extend between the channel region and the source region and the drain region, and also below a portion of the gate electrode, that have a third peak dopant concentration higher than the first peak dopant concentration and lower than the second peak dopant concentration by one order of magnitude or more.
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Patent Owner(s)
- TOSHIBA MEMORY CORPORATION
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Noguchi, Mitsuhiro | Yokkaichi Mie, JP | 160 | 3669 |
Tomino, Hirokazu | Yokkaichi Mie, JP | 2 | 7 |
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