Method to Improve Charge Trap Flash Memory Top Oxide Quality

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United States of America Patent

SERIAL NO

14270700

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Abstract

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A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

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Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHEN, Tung-Sheng Cupertino, US 17 65
FANG, Shenqing Fremont, US 127 886
KANG, Inkuk San Jose, US 26 312

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