INTERFACES WITH BUILT-IN TRANSIENT VOLTAGE SUPPRESSION
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United States of America Patent
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Issued Date -
Sep 10, 2015
app pub date -
Mar 4, 2014
filing date -
Mar 4, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An interface for protecting electronic devices from external Electric Over-Stress (EOS), Electromagnetic Interference (EMI) and Electrostatic Discharge (ESD) is disclosed. The interface is coupled to a PCB having electronic circuits. The interface device comprises a plurality of conducting lines for establishing electrical communication with the circuits on the PCB, wherein each conducting line has a distinct potential; and protection components connected to the conducting lines in the interface to shunt the EOS/EMI/ESD energy therethrough in the event of EOS occurring on the conducting lines.
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