Storage device, memory controller and memory control method
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United States of America Patent
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Jan 12, 2016
Grant Date -
Sep 10, 2015
app pub date -
Jun 17, 2014
filing date -
Mar 10, 2014
priority date (Note) -
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Abstract
According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.
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